A conventional integrated circuit package power supply circuit comprises power supply lines which typically provide an operating voltage VDD and a ground voltage VSS. Normally, the power consumption of an integrated circuit is not constant but changes while the integrated circuit is in operation. One reason for a strong power consumption change is a switching of output signals. Especially, such strong changes in the power consumption result in a voltage noise on the power supply lines. Integrated circuits, like memory chips, which operate at high frequencies and low operating voltages, react very sensitive to voltage swings. Thus, the voltage noise on the power supply lines may cause a failure in the operation of the integrated circuit.
FIG. 1 shows a schematic view of a prior art integrated circuit power supply circuit. The circuit comprises an output stage of an integrated circuit chip 102. The output stage is a “push-pull” output stage, which is typically used for memory chips. The output stage comprises a means for switching 104, a first supply line 106, a second supply line 108, a signal line 110 and a power supply 112 which provides an operating voltage VDD and a ground voltage VSS. The integrated circuit chip 102 and the power supply 112 are typically arranged on a printed circuit board (not shown in FIG. 1). The integrated circuit chip 102 comprises terminals 120, 122, 124 for connecting the integrated circuit chip 102 to the circuit board. The terminals 120, 122, 124 typically are pins or balls.
The first supply line 106 provides the operating voltage VDD from the power supply 112 via the first terminal 120 to the means for switching 104. The second supply line 108 provides the ground voltage VSS from the power supply 112 via the second terminal 122 to the means for switching 104. The signal line 110 is connected to the third terminal 124 and via a pull-up resistor 126 to the first supply line 106. The signal line 110, which is an output line, is connected to a second circuit (not shown).
The means for switching 104 switches the signal voltage on the signal line 110 between the operating voltage VDD and the ground voltage VSS. The means 104 for switching comprises a first transistor 130, a second transistor 132 and a bit source signal 134. The bit source signal 134 is an output of an internal circuit of the integrated circuit chip 102 and controls the signal voltage on the signal-line 110. In a first state, the bit source signal 134 causes the second transistor 132 to close and the first transistor 130 to open and to connect the signal line 110 to the first supply line 106. In this state, the signal voltage on the signal line 110 switches to the operating voltage VDD. In a second state, the bit source signal 134 causes the first transistor 130 to close and the second transistor 132 to open and to connect the signal line 110 to the second supply line 108. Thus, the signal voltage on the signal line 110 switches to the ground voltage VSS.
The inductances 140, 142, 144 are models for the typical inductances of the lines 106, 108, 110. The first supply line 106 and the second supply 108 are decoupled by an in-chip power supply decoupling circuitry, which is modelized by the capacitor 146. In the existing kinds of integrated circuit packages, the inductances 140, 142 of power supply package traces 106, 108 make a large voltage noise due to a high current slew rate across the inductances 140, 142 during the switching of the transistors 130, 132.
FIG. 2 shows a package power supply routing according to the prior art, comprising an integrated circuit chip 201 which is arranged on a circuit package board 202. The integrated circuit chip 201 is connected via a first bond wire 206′ to a first supply line 206, via a second bond wire 208′ to a second supply line 208 and via a third bond wire 210′ to a signal line 210. The supply lines 206, 208 and the signal line 210 correspond to the respective lines shown in FIG. 1. The first supply line 206 is connected to a first terminal 220 of the package board 202, the second supply line 208 connected to a second terminal 222 and the signal line 210 connected to a third terminal 224. Typically the supply lines 206, 208 supply a plurality of output stages or drivers of the integrated circuit chip 201. Therefore, the resulting current on the supply lines 206, 208 is higher than the current on the signal line 210. In order to achieve a high current slew rate on the supply lines 206, 208, the supply lines 206, 208 are typically wider than the signal line 210. This reduces the inductance and resistance of the supply lines 206, 208. An additional reason for this is that in most cases, in an IC package, a pair of supply pins provides a current to more than one, typically to two to four drivers.
Here the integrated circuit chip 201 is a memory chip. The lines 206, 208, 210 are printed circuit board lines on the circuit package board 202 of the memory chip 201 and the terminals 220, 222, 224 are pins or balls, which connect the circuit package board 202 to a memory module (not shown). The signal line 210 is a data quit trace connected to an output driver (not shown in FIG. 2) of the memory chip 201.
FIG. 3 shows a cross-section through a part of the circuit package board 202 and the first supply line 206 shown in FIG. 2. The supply line 206 is formed by a copper trace which is arranged on the circuit package board 202. A surface of the circuit package board 202, opposite to the supply line 206 is covered by a ground plane 202′. In this embodiment a height 300 of the circuit package board 202 is 100 mil or 2.54 mm (1 mil is 1/1000 of 1 inch), a height 302 of the copper trace 206 is 1 mil or 0.0254 mm, the width 304 of the copper trace 206 is 2 mil and the length 306 of the copper trace 206 is 200 mil or 5.08 mm. The dielectric constant Er is 4.5.
FIG. 4 shows a simulation result of the circuit shown in FIG. 1. The simulation tool “Advanced Design Studio”, simulator version 2000C was used for simulation. A model for the supply lines 106, 108 is shown in FIG. 3. The driver output resistance of the means for switching 104 is assumed as Ron=20 Ohm, the output signal rise/fall time from 10% to 90% as Trf=325 ps for the signal line 110, the bit-rate of the signal line 110 is 1.6 Gbps, the termination resistance of the termination resistor 126 is R1=30 Ohm, the power supply voltage VDD is 1.8V and the internal power decoupling capacitor has a capacity of C1=500 pF.
The characteristics 440, 442, 444 shown in FIG. 4 represent the voltage levels on the lines 106, 108, 110 over the time. The characteristic 440 corresponds to the voltage level on the first supply line 106, the characteristic 442 corresponds to the voltage level on the second supply line 108 and the characteristic 444 corresponds to the voltage level of the signal line 110. In the beginning, the voltages on the signal line 110 and the first supply line-106 are stable at 1.8V. The voltage on the second supply line 108 is stable at 0V. After Ins the bit source signal 134 switches and causes the first transistor 130 to close and the second transistor 132 to open. Consequently, the voltage on the signal line 110 switches to a low level. Due to the output resistance of the second transistor 132, the characteristic 444 does not drop down to 0V but settles at approximately 0.7V. After 2 ns the bit source signal 134 again switches and causes the first transistor 130 to open and the second transistor 132 to close. Consequently the characteristic 444 of the signal line-110 rises again. As can be seen from FIG. 4, the characteristics 440, 442 of the supply lines 106, 108 are not stable at 1.8V and 0V but are affected by the switching voltage of the signal line 110, represented by the characteristic 444. The simulation results show an unacceptable high ground and VDD bounce on the characteristics 440, 442. This voltage swing has an upper peak value 450 of 0.256 V above the VDD voltage of 1.8V and a lower peak value 452 of 0.272V below the normal ground voltage of 0V. A maximum difference of the voltage level of the characteristics 440, 442 is 0.067V. Thus, the voltage swing is approximately 15% of the supply voltage value. Thus, even though the supply lines 206, 208 are formed as wide copper traces, as shown in FIG. 2, the voltage noise on the supply lines 206, 208 is too high for a secure operation of an integrated circuit like a memory chip.
To reduce the voltage noise on the power supply lines, additional power supply lines are necessary or the existing power supply lines have to be designed still wider. Because of space limitations on the circuit package board 202, such solutions are often not realizable.